1. Field of the Invention
The present invention relates to a semiconductor device, a method of manufacturing the same and a method of designing the same. More particularly, the present invention is suitable for a semiconductor device manufactured by a method including a flattening step employing a chemical mechanical polishing process (CMP process).
2. Background Art
When manufacturing recent semiconductor devices, it is difficult to form a minute wiring pattern on a greatly stepped interlayer insulating film and improvement of the planarity of the interlayer insulating film has been necessary. A global flattening method employing a CMP process has become prevalently used in recent years. When using the flattening method employing the CMP process, a dummy pattern for CMP must be formed in a wiring layer underlying an interlayer insulating film to be subjected to the CMP process to avoid dishing.
Dishing is the variation of a layer insulting film polishing characteristic according to the line density of a wiring layer underlying the interlayer insulating film. When dishing occurs, portions of the interlayer insulating film overlying regions in which wiring lines are not formed of the wiring layer or regions in which wiring lines are formed at a low line density are polished by a polished amount greater than that by which portions of the interlayer insulating film overlying regions in which wiring lines are formed in a high line density of the wiring layer are polished. If dishing occurs, the surfaces of portions of the interlayer insulating film overlying the regions of the wiring layer in which wiring lines are formed in high line densities are polished excessively with the proceeding of polishing and, if the worst comes to the worst, the underlying wiring layer is polished to deteriorate the wiring pattern of the wiring layer.
The dummy pattern for CMP is formed to make uniform line density in the wiring layer underlying the interlayer insulating film to be polished. Thus, dishing can be suppressed and the deterioration of the planarity of the interlayer insulating film can be prevented by forming the dummy pattern in predetermined regions in addition to the wiring pattern necessary for the operation of the semiconductor device.
However, chips in a semiconductor wafer are separated from each other by dicing regions. Since the dummy pattern cannot be formed in the dicing regions, the planarity of parts of the interlayer insulating film near the dicing regions are unsatisfactory.
This problem will be described with reference to FIGS. 7 and 8. FIGS. 7 and 8 show a part of a semiconductor wafer having chips provided with semiconductor devices in a state before being processed by a dicing process, in which semiconductor elements are formed on the semiconductor wafer, a wiring layer 100 is formed, and a interlayer insulting film 101 is formed on the wiring layer 100. The wiring layer 100 shown in FIGS. 7 and 8 is an (n)th (n is a natural number) wiring layer of a semiconductor device among a plurality of wiring layers, and the other wiring layers are omitted. FIG. 7 is a plan view and FIG. 8 is a sectional view of the semiconductor device. FIG. 8A is a sectional view taken on line III-IIIxe2x80x2 in FIG. 7 and FIG. 8B is a sectional view taken on line IV-IVxe2x80x2 in FIG. 7. In FIG. 7, the interlayer insulating film 101 is omitted to facilitate understanding.
As shown in FIG. 8A, the respective line densities of an (n)th layer dicing region, a chip wiring region and a CMP dummy pattern region in the vicinity of a dicing region in which an alignment mark is formed in the wiring layer 100 are nearly equal to each other, and hence the difference between parts of the interlayer insulating film 101 respectively corresponding to those regions in polished amount by which the interlayer insulating film will be removed by the CMP process is small.
As shown in FIG. 8B, any wiring pattern consists of the wiring layer 100 cannot be formed in parts corresponding to the dicing region. Therefore, the line density in the dicing region is very small as compared with those in the chip wiring region, the CMP dummy pattern region and a chip frame region. Consequently, the polished amount by which the interlayer insulating film 101 is removed by the CMP process increases gradually from the chip wiring region toward the dicing region and the chip wiring lines 100a nearest to the dicing region are polished to deteriorate the patterns of the chip wiring lines 100a, resulting in deterioration of the wiring pattern and the resultant reduction of the reliability of the device.
The present invention has been made to solve such a problem and it is therefore a first object of the present invention to provide a semiconductor device, a method of manufacturing the semiconductor device and a method of designing the semiconductor device that enable the further improvement of the planarity in a peripheral part of a chip when a flattening step employing a CMP process is used.
A second object of the present invention is to improve the construction of a peripheral part of a chip provided with a screening pattern for flattening.
According to one aspect of the present invention, a semiconductor device comprises a plurality of superposed layers on a semiconductor substrate including a predetermined layer provided, in a peripheral part of a chip, with a dummy pattern of a material that is the same as that forming a wiring pattern formed in the same predetermined layer. The dummy pattern is formed on an inner side of a dicing region. The ratio of an area of the dummy pattern in a planar region defined by an inner edge of the dummy pattern, an outer edge of the dicing region and two optional, parallel lines to that of the planar region is 50% or above.
According to another aspect of the present invention, a method of manufacturing a semiconductor device, a wiring layer is formed over an insulating film formed on a semiconductor substrate firstly. Secondly, parts of the wiring layer is selectively removed to form a predetermined wiring pattern and a dummy pattern on an inner side of a dicing region in a peripheral part of a chip, and setting an area of the dummy pattern so that the ratio of an area of the dummy pattern in a planar region defined by an inner edge of the dummy pattern, an outer edge of the dicing region and two optional, parallel lines to that of the planar region is 50% or above. An interlayer insulating film is formed over the insulating film so as to cover the wiring pattern and the dummy pattern thirdly. A surface of the interlayer insulating film is plnarized by polishing fourthly.
According to another aspect of the present invention, a method of designing a semiconductor device, a predetermined wiring pattern and a predetermined dummy pattern is respectively arranged from a predetermined wiring layer formed on a semiconductor substrate on an inner side of a dicing region in a peripheral part of a chip firstly. The ratio of an area of the dummy pattern in a planar region defined by an outer edge of the dicing region, an inner edge of the dummy pattern and two optional, parallel lines to that of the planar region is calculated secondly. The ratio of the area of the dummy pattern is compared with that of the planar region with a predetermined threshold thirdly. The area of the dummy pattern is increased when the ratio of the area of the dummy pattern to that of the planar region is smaller than the predetermined threshold fourthly.
According to the present invention, when the surface of the interlayer insulating film is polished by a CMP process for planarization, the planarity of the peripheral part of the chip can be further improved and the deterioration of the wiring pattern in the peripheral part of the chip can be suppressed because the size of the dummy pattern is determined so that the line density in the specified planar region is 50% or above.
Other and further objects, features and advantages of the invention will appear more fully from the following description.